1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a thin film magnetic memory device capable of random access and including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the performance of the MRAM device is significantly improved by using tunnel magnetic resistive elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 39 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as “MTJ memory cell”).
Referring to FIG. 39, the MTJ memory cell includes a magnetic tunnel junction MTJ having its electric resistance value varying according to the storage data level, and an access transistor ATR. The access transistor ATR is formed from a field effect transistor, and is connected in series with the magnetic tunnel junction MTJ between the bit line BL and the ground voltage VSS.
For the MTJ memory cell are provided a write word line WWL for instructing data write operation, a read word line RWL for instructing data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the storage data level in the data read and write operations.
FIG. 40 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 40, the magnetic tunnel junction MTJ has a magnetic layer FL having a fixed magnetization direction (hereinafter, also simply referred to as “fixed magnetic layer”), and a magnetic layer VL having a free magnetization direction (hereinafter, also simply referred to as “free magnetic layer”). A tunnel barrier TB of an insulator film is formed between the fixed magnetic layer FL and the free magnetic layer VL. The free magnetic layer VL has been magnetized in the direction corresponding to the storage data level, i.e., either in the same direction as that of the fixed magnetic layer FL or the direction different therefrom.
In the data read operation, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed from the bit line BL, magnetic tunnel junction MTJ and ground voltage VSS. The sense current Is is supplied as a constant current from a not-shown control circuit.
The electric resistance value of the magnetic tunnel junction MTJ varies according to the relative relation of the magnetization direction between the fixed magnetic layer FL and the free magnetic layer VL. More specifically, when the fixed magnetic layer FL and the free magnetic layer VL have the same magnetization direction, the magnetic tunnel junction MTJ has a smaller electric resistance value as compared to the case where both magnetic layers have different magnetization directions.
In the data read operation, a voltage change produced at the magnetic tunnel junction MTJ by the sense current Is varies depending on the magnetization direction stored in the free magnetic layer VL. Therefore, by starting supply of the sense current Is after precharging the bit line BL to a high voltage, the storage data level in the MTJ memory cell can be read by sensing a change in voltage level on the bit line BL.
FIG. 41 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 41, in the data write operation, the read word line RWL is inactivated, whereby the access transistor ATR is turned OFF. In this state, a data write current for generating a data write magnetic field for magnetizing the free magnetic layer VL in the direction corresponding to the storage data level is applied to the write word line WWL and the bit line BL. The magnetization direction of the free magnetic layer VL is determined by combination of the respective directions of the data write currents flowing through the write word line WWL and the bit line BL.
FIG. 42 is a conceptual diagram illustrating the relation between the direction of the data write current and the direction of the data write magnetic field in the data write operation.
Referring to FIG. 42, a magnetic field Hx of the abscissa indicates the direction of a data write magnetic field H(WWL) generated from the data write current flowing through the write word line WWL. A magnetic field Hy of the ordinate indicates the direction of a data write magnetic field H(BL) generated from the data write current flowing through the bit line BL.
The magnetization direction of the free magnetic layer VL is updated only when the sum of the data write magnetic fields H(WWL) and H(BL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetization direction of the free magnetic layer VL is not updated when a data write magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to write the storage data to the MTJ memory cell, a data write current must be applied to both write word line WWL and bit line BL. Once stored in the magnetic tunnel junction MTJ, the magnetization direction, i.e., the storage data level, is retained therein in a non-volatile manner until another data write operation is conducted.
A sense current Is flows through the bit line BL in the data read operation. However, the sense current Is is generally set to a value that is about one to two orders smaller than the data write current. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten by the sense current Is during the data read operation.
The aforementioned technical documents disclose the technology of forming an MRAM device, a random access memory, with such MTJ memory cells being integrated on a semiconductor substrate.
FIG. 43 is a conceptual diagram showing the MTJ memory cells arranged in a matrix in an integrated manner.
Referring to FIG. 43, with the MTJ memory cells arranged in a matrix on the semiconductor substrate, a highly integrated MRAM device can be realized. FIG. 43 shows the case where the MTJ memory cells are arranged in n rows by m columns (where n, m is a natural number). Herein, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are arranged for the n×m MTJ memory cells.
In the data read operation, one of the read word lines RWL1 to RWLn is selectively activated, so that the memory cells on the selected memory cell row (hereinafter, also simply referred to as “selected row”) are electrically coupled between the bit lines BL1 to BLm and the ground voltage VSS, respectively. As a result, the voltage on each bit line BL1 to BLm changes according to the storage data level in a corresponding memory cell.
Thus, the storage data level of the selected memory cell can be read by comparing the voltage on the bit line of the selected memory cell row (hereinafter, also simply referred to as “selected column”) with a prescribed reference voltage using a sense amplifier or the like.
In such a data read operation, however, a path of the sense current Is is formed in every memory cell on the selected row. Therefore, a wasteful charging/discharging current that does not directly contribute to the data read operation is produced in the bit lines of the non-selected memory cell columns (hereinafter, also simply referred to as “non-selected columns”), thereby increasing the power consumption in the data read operation.
As described in the aforementioned technical documents, as the bias voltage applied to both ends of the magnetic tunnel junction is increased, the relative relation of the magnetization direction between the fixed magnetic layer FL and the free magnetic layer VL, i.e., a change in electric resistance value corresponding to the storage data level, is less likely to appear. Therefore, as the voltage applied to both ends of the magnetic memory cell is increased in the data read operation, the voltage on the bit line does not noticeably change according to the storage data level. This may possibly hinder the speed and stability of the data read operation.
Moreover, a dummy memory cell is generally used to produce a reference voltage to be compared with a voltage on the bit line coupled to the selected memory cell. For example, a resistive element having an electric resistance value Rd corresponding to an intermediate value of electric resistance values R1 and R0 can be used as a dummy cell for use in the data read operation to the MTJ memory cell. The electric resistance values R1 and R0 respectively correspond to the case where the data “1 (H level)” and “0 (L level)” are stored in the MTJ memory cell. The reference voltage can be produced by supplying to such a resistive element the same sense current Is as that supplied to the MTJ memory cell.
In general, the dummy memory cells are arranged in a dummy row or dummy column.
When the dummy memory cells are arranged in a dummy row, the data read operation can be conducted based on a so-called folded bit line structure by using a bit line pair of adjacent two bit lines. In this structure, the selected MTJ memory cell and the dummy memory cell can be respectively coupled to the adjacent two bit lines. Accordingly, the respective RC (resistance-capacitance) time constants between the selected MTJ memory cell and dummy memory cell and the sense amplifier have the same value, whereby a read operation margin can be ensured.
In this case, however, the sense current must be supplied also to the dummy memory cells on the non-selected memory cell columns, thereby increasing the power consumption in the data read operation.
On the contrary, when the dummy memory cells are arranged in a dummy column, the sense current need not be supplied to a plurality of dummy memory cells. However, a bit line to be coupled to the selected MTJ memory cell cannot necessarily be located near a dummy bit line of the dummy column to be coupled to the dummy memory cell. This may degrade the read operation margin or reduce the data read operation since the respective RC time constants between the selected MTJ memory cell and dummy memory cell and the sense amplifier have different values.
As described before, the data write operation to the MTJ memory cell is conducted with combination of the data write magnetic fields respectively generated from the data write currents flowing through the write word line WWL and the bit line BL. Accordingly, the data write current must be supplied so as to effectively and stably magnetize the free magnetic layer VL in the magnetic tunnel junction MTJ.
The data write magnetic field applied to the selected MTJ memory cell acts as magnetic noise on adjacent MTJ memory cells. Therefore, erroneous data write operation to a memory cell other than the selected memory cell must be prevented. In particular, reducing a data write current required to generate a prescribed magnetic field for the data write operation would implement reduced power consumption as well as stabilized operation due to suppressed magnetic noise.